1. Field of the Invention
The present invention relates to the field of computer systems and associated memory structures. More particularly, the present invention relates to a bus architecture designed specifically for integrating data and video random access memory (RAM) modules.
2. Art Background
General purpose computer systems usually contain one or more buses for interconnecting the various active components operating within the computer system. A bus may be generally described as a group of signal lines over which information is transferred from any of several sources to any of several destinations. Physically, a bus is a collection of wires routed on the computer motherboard and terminating at sockets into which may be inserted a variety of active devices. The active devices are usually constructed in modular form and generate and receive the signals transmitted over the collection of wires forming the bus. Well known bus systems include VME bus.RTM., microchannel.RTM., multibus.RTM., MBus, and SBus.
Typically, devices communicating over a bus utilize a set of control signals referred to collectively as a bus protocol to coordinate transfer of signals transmitted over the bus. Many of such control signals are common to each of the above named bus systems and to bus systems generally. However, most bus protocols further include a number of specific control signals permitting manipulation of data transmitted over the bus in a manner unique to the particular bus employing such signal. For example, some buses may be particularly designed to accommodate a number of bus masters, and which bus operation must accommodate signals issued by the masters seeking to control any of several slaves operating on the bus. Alternatively, another bus may be more generally designed to accommodate any of several arbitrary devices operating on the bus, and does not favor any particular operating characteristics of the devices connected to the bus. Further, all buses are constrained to operate within the physical design limits of the bus, in terms of bandwidth, data rate, and clock frequency.
Also in the past, memory devices operating on a bus were typically grouped into modules according to the type of memory function to be served. Typically, one form of memory, for example main memory, would be coupled to the bus to which is connected the processor, or processors in a multiprocessing system processors. Depending on the specific organization of such a computer system, additional memory components forming memory for other purposes, such as non-volatile memory or memory dedicated to video frame buffers, may be grouped into modules coupled to buses other than the bus connecting main memory to the processors. Further, additional memory may be later added to a computer system and be grouped onto yet a different bus.
In such a computer system having memory distributed over a number of buses, access to the various memory modules can be hampered by the number of data paths, controllers and interface chips through which signals must travel from a processor seeking to retrieve or write data from or to a memory device operating on a remote bus system. Moreover, having distributed memory modules requires more area within the computer system in order to accommodate the several bus data paths and memory groupings. Another consequence of having distributed memory groupings is that the memory modules inserted in such a memory group are specific to that memory group and cannot be interchanged with memory modules from another grouping. That is to say, a memory module from main memory generally cannot be interchanged with a memory module for a video frame buffer operating on a different bus, principally because the control signals to the video frame buffer memory are different from the control signals directed to the main memory module. The generic problem in all of these various distributed bus systems is that the number of signal lines to accommodate the various types of control signals and signal conditions can become large. This adds to the general complexity, and therefore the cost and reliability of the overall computer system.